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arch/arm/lib/relocate.S

/*
 * Default/weak exception vectors relocation routine
 *
 * This routine covers the standard ARM cases: normal (0x00000000),
 * high (0xffff0000) and VBAR. SoCs which do not comply with any of
 * the standard cases must provide their own, strong, version.
 */

        .section        .text.relocate_vectors,"ax",%progbits
        .weak           relocate_vectors

ENTRY(relocate_vectors)

#ifdef CONFIG_CPU_V7M
        /*
         * On ARMv7-M we only have to write the new vector address
         * to VTOR register.
         */
        ldr     r0, [r9, #GD_RELOCADDR] /* r0 = gd->relocaddr */
        ldr     r1, =V7M_SCB_BASE
        str     r0, [r1, V7M_SCB_VTOR]
#else
#ifdef CONFIG_HAS_VBAR
        /*
         * If the ARM processor has the security extensions,
         * use VBAR to relocate the exception vectors.
         */
        ldr     r0, [r9, #GD_RELOCADDR] /* r0 = gd->relocaddr */
        mcr     p15, 0, r0, c12, c0, 0  /* Set VBAR */
#else
        /*
         * Copy the relocated exception vectors to the
         * correct address
         * CP15 c1 V bit gives us the location of the vectors:
         * 0x00000000 or 0xFFFF0000.
         */
        ldr     r0, [r9, #GD_RELOCADDR] /* r0 = gd->relocaddr */
        mrc     p15, 0, r2, c1, c0, 0   /* V bit (bit[13]) in CP15 c1 */
        ands    r2, r2, #(1 << 13)
        ldreq   r1, =0x00000000         /* If V=0 */
        ldrne   r1, =0xFFFF0000         /* If V=1 */
        ldmia   r0!, {r2-r8,r10}
        stmia   r1!, {r2-r8,r10}
        ldmia   r0!, {r2-r8,r10}
        stmia   r1!, {r2-r8,r10}
#endif
#endif
        bx      lr

ENDPROC(relocate_vectors)

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